The present invention relates generally to a semiconductor device and a method of operating the same, and more particularly relates to a semiconductor device including memory cells and a method of operating the same.
A semiconductor memory device may be classified into a volatile memory device or a non-volatile memory device.
In the volatile memory device, the memory cell maintains the stored data even if power is not supplied. A representative non-volatile semiconductor memory device is a NAND flash memory device.
The NAND flash memory device stores 2 bits of data in a memory cell. Accordingly, if a program operation for storing data in memory cells is completed, threshold voltages of the memory cells have an erase level, and a first to a third program levels. In a read operation, voltages between threshold voltage distributions are used as a read voltage so as to classify the threshold voltages of the memory cells.
Since the distance between memory cells becomes narrower to enhance integrity and interference occurs between adjoining memory cells, data read according to the read operation includes error bits. The error bits may be corrected through an error correction code (ECC) unit when the number of error bits is smaller than a preset value, but errors may occur when the number of error bits is higher than the preset value.
Accordingly, a method of minimizing the number of error bit in a data read operation from the memory cells has been required.